As is well known, memory cells arranged in a matrix format of rows and columns are provided in semiconductor memory devices. In order to write/read data to/from any memory cells, rows and columns should be selected. In other words, semiconductor memory devices should have a circuit for selecting rows (hereinafter referred to as “a row decoder circuit”) and a circuit for selecting columns. The larger a memory capacity is, the greater the number of memory cells connected to a row/column. That is, now that a load of the row/column is increased, a time for driving the row/column leads to an increment of an access time. To overcome these problems, various techniques have been suggested recently. A typical example is a hierarchical row/column structure. A row decoder circuit with the hierarchical row/column structure is disclosed in Korean Laid-Open Publication No. 10-2004-0015901, which is hereby incorporated by reference.
FIG. 1 is a circuit diagram showing a row decoder circuit in a non-volatile memory device according to a conventional art. The decoder circuit of FIG. 1 is carried in the above-mentioned Korean Laid-Open Publication. The decoder circuit of FIG. 1 is a local decoder circuit corresponding to one global word line GWL. It will be clearly understood by those skilled in the art that local decoder circuits corresponding to the rest of the global word lines are constructed in the same manner. During an erase operation, the local decoder circuit of FIG. 1 is explained as follows.
An erase voltage of about −10V should be provided to word lines WL0-WLi during the erase operation. For this, while selection signals SS and GWL are maintained in a low level, Vpx, Vpgate, and Vex are set to 0V, −2V, and −10V, respectively. Under this bias condition, ND1 node is set to 0V by a PMOS transistor 11. These word lines WL0-WLi are respectively set to Vex, by NMOS transistors 12_0-12_i. That is, the word lines WL0-WLi are driven −10V, respectively during the erasing operation. Memory cells connected to the word lines WL0-WLi will be erased in well-known manner.
As previously mentioned, −2V Vpgate should be provided to the local decoder circuit 10 according to the conventional art during the erase operation. This means that a leased pump for generating −2V as well as a circuit for controlling the leased pump is required to non-volatile memory devices.